coreboot-kgpe-d16/src/mainboard/google/hatch
Kyösti Mälkki cf246d5166 ACPI: Add top-level ASL
Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.

There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.

Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-27 15:35:13 +00:00
..
spd
variants mb/google/nightfury: Update RAM IDs usage 2021-01-22 14:27:15 +00:00
board_info.txt
bootblock.c mb/google/hatch: do UART pad configuration at board-level 2021-01-21 17:52:06 +00:00
chromeos-hatch-16MiB.fmd
chromeos-hatch-32MiB.fmd
chromeos-puff-16MiB.fmd
chromeos-puff-32MiB.fmd
chromeos.c
dsdt.asl ACPI: Add top-level ASL 2021-01-27 15:35:13 +00:00
ec.c
Kconfig soc/intel/common/cse: Drop dependency on CHROMEOS for SOC_INTEL_CSE_LITE_SKU 2021-01-07 08:16:12 +00:00
Kconfig.name hatch: Create genesis variant 2020-11-09 10:18:07 +00:00
Makefile.inc arch/x86: Use wildcard for mb/smihandler.c 2021-01-24 21:06:22 +00:00
ramstage.c soc/intel/cannonlake: Change mainboard_silicon_init_params argument 2020-12-17 06:22:55 +00:00
romstage_spd_cbfs.c
romstage_spd_smbus.c src: Add missing 'include <console/console.h>' 2020-11-17 09:01:14 +00:00
smihandler.c