coreboot-kgpe-d16/src
Elyes HAOUAS 2164c308b4 include/device/dram/ddr3.h: Don't redefine 'printram(x, ...)'
'printram(x, ...)' is already defined in 'include/device/dram/common.h' file

Change-Id: I75e19065b9e713df3190202b7ca9e9cd8f3f44a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-21 15:23:12 +00:00
..
acpi src/acpi/acpigen.c: Reformat code 2022-02-21 15:19:24 +00:00
arch arch/x86/id.S: Fix building with clang 2022-02-15 23:36:33 +00:00
commonlib compiler.h: Define a __fallthrough statement 2022-02-16 21:28:09 +00:00
console Use the fallthrough statement in switch loops 2022-02-16 21:29:53 +00:00
cpu cpu/x86/lapic: Fix SMP=n case with LEGACY_SMP_INIT 2022-02-11 13:53:56 +00:00
device device: Add support for PCIe Resizable BARs 2022-02-16 20:19:07 +00:00
drivers drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs 2022-02-18 20:21:45 +00:00
ec arch/x86/acpi: Add code for KEY_MENU 2022-02-18 20:18:41 +00:00
include include/device/dram/ddr3.h: Don't redefine 'printram(x, ...)' 2022-02-21 15:23:12 +00:00
lib Use the fallthrough statement in switch loops 2022-02-16 21:29:53 +00:00
mainboard mb/google/brya/variants/felwinter: Adjust I2Cs CLK to be around 400 kHz 2022-02-21 15:21:28 +00:00
northbridge nb/amd/pi/00730F01/northbridge.c: Use 'pci_{and,or}_config' 2022-02-18 23:23:07 +00:00
security treewide: Remove "ERROR: "/"WARN: " prefixes from log messages 2022-02-07 23:29:09 +00:00
soc soc/intel/denverton_ns: Add pmc_mmio_regs as public function 2022-02-21 15:22:35 +00:00
southbridge src/acpi: Add macro for FADT Minor Version and use it 2022-02-21 15:16:37 +00:00
superio Use the fallthrough statement in switch loops 2022-02-16 21:29:53 +00:00
vendorcode vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v2503_00 2022-02-16 20:17:46 +00:00
Kconfig Kconfig: Show console DEBUG_FUNC if OVERRIDE_LOGLEVEL is set 2021-11-13 00:20:11 +00:00