Felix Held 3fe1ad1f26 soc/amd/stoneyridge/reset: use port and bit defines from cf9_reset.h ... The register name and the name of one bit are slightly different, but have the same functionality. Change-Id: Ie49975bb43868cbb2dc986e66dc5b7291e70222f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48507 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-12-10 16:00:55 +00:00
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amd	soc/amd/stoneyridge/reset: use port and bit defines from cf9_reset.h	2020-12-10 16:00:55 +00:00
cavium	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
example	x86: Add a minimal example SoC along with a board	2020-10-30 21:34:18 +00:00
intel	mb/intel/ehlcrb: Add EHL CRB memory initialization support	2020-12-10 10:49:15 +00:00
mediatek	soc/mediatek/mt8192: Init SSPM	2020-12-10 14:05:27 +00:00
nvidia	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
qualcomm	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
rockchip	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
samsung	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
sifive	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
ti	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
ucb