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coreboot-kgpe-d16/src/mainboard/intel/shadowmountain
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Kyösti Mälkki 9a3bde0581 ChromeOS: Replace with or add <types.h> 
It's commented in <types.h> that it shall provide <commonlib/helpers.h>.

Fix for ARRAY_SIZE() in bulk, followup works will reduce the number
of other includes these files have.

Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11 06:25:12 +00:00
..
spd mb/intel/shadowmountain: Add the romstage code 2021-02-22 05:46:58 +00:00
variants/baseboard ChromeOS: Replace with or add <types.h> 2021-11-11 06:25:12 +00:00
board_info.txt
bootblock.c mb/intel/shadowmountain: Add bootblock and verstage code 2021-02-06 09:09:16 +00:00
chromeos.c ChromeOS: Replace with or add <types.h> 2021-11-11 06:25:12 +00:00
chromeos.fmd mb/intel/shadowmountain: Add flash layout 2021-01-28 03:11:35 +00:00
dsdt.asl mb/intel/shadowmountain: Add the ASL code 2021-02-27 09:40:57 +00:00
ec.c mb/intel/shadowmountain: Add the ramstage code 2021-02-27 09:40:47 +00:00
Kconfig src/*: Specify type of DIMM_SPD_SIZE once 2021-09-03 00:10:33 +00:00
Kconfig.name
mainboard.c mb/intel/shadowmountain: Add the ramstage code 2021-02-27 09:40:47 +00:00
Makefile.inc mb/intel/shadowmountain: Add the ramstage code 2021-02-27 09:40:47 +00:00
romstage.c soc/intel/alderlake: Update mainboard_memory_init_params() argument 2021-06-24 07:55:12 +00:00
smihandler.c mb/intel/shadowmountain: Add the ramstage code 2021-02-27 09:40:47 +00:00