Jakub Czapiga 43b7e60e3e Revert "mb/google/brya: Add romstage early graphics for brya" ... This reverts commit 96d9b75669. Reason for revert: Merged out of order, broke tree Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Iac2d78f2d6c687f52dc720e8d8dcb5cf7a171c9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71280 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2023-01-04 20:30:38 +00:00
..
acpi	tree/acpi: Replace constant "Zero" with actual number	2022-12-27 09:06:47 +00:00
arch	{acpi,arch,soc}/acpi: Replace constant "One" with actual number	2022-12-27 09:05:15 +00:00
commonlib	coreboot_tables: Make existing alignment conventions more explicit	2022-12-22 15:34:28 +00:00
console	lib: Hook up libhwbase in romstage	2022-12-17 20:51:38 +00:00
cpu	cpu/x86: Set up a separate stack for APs	2022-12-23 14:29:01 +00:00
device	spd.h: Move enum ddr3_module_type to ddr3.h	2023-01-04 12:39:32 +00:00
drivers	drivers/pc80/vga: Add API to write multi-line video message	2023-01-02 05:45:23 +00:00
ec	{ec,mb}/system76/acpi: Use Printf() for debug prints	2022-12-29 16:30:15 +00:00
include	spd.h: Move enum ddr3_module_type to ddr3.h	2023-01-04 12:39:32 +00:00
lib	coreboot_tables: Make existing alignment conventions more explicit	2022-12-22 15:34:28 +00:00
mainboard	Revert "mb/google/brya: Add romstage early graphics for brya"	2023-01-04 20:30:38 +00:00
northbridge	spd.h: Move enum ddr3_module_type to ddr3.h	2023-01-04 12:39:32 +00:00
sbom
security	security/intel/stm/StmPlatformResource.c: Fix typo on "threads"	2022-12-31 09:30:54 +00:00
soc	soc/intel: Create common function to check PCH slot	2023-01-04 14:12:29 +00:00
southbridge	sb/intel/lynxpoint: Add Kconfig option to hide Intel ME	2022-12-23 14:20:39 +00:00
superio	{superio,ec}/acpi: Replace constant "Zero" with actual number	2022-12-27 09:06:29 +00:00
vendorcode	soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimization	2023-01-04 07:15:10 +00:00
Kconfig