Angel Pons 4500893062 nb/intel/ironlake: Correct PCIEXBAR definition ... This register resides within the SAD's config space, and is 64-bit. Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>		2020-08-03 05:30:59 +00:00
..
acpi	src/acpi: Add missing <{stdbool,stdint}.h>	2020-07-29 09:37:10 +00:00
arch	mb/emulation/qemu-armv7: Fix board	2020-08-03 05:11:17 +00:00
commonlib	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
console	console: Update for vboot before bootblock	2020-06-15 22:07:12 +00:00
cpu	cpu/intel/haswell: add Crystal Well CPU IDs	2020-08-03 05:16:29 +00:00
device	Change all assert(0) to BUG()	2020-08-03 05:15:15 +00:00
drivers	drivers/ipmi/ocp: Add ipmi set processor information	2020-08-03 05:24:27 +00:00
ec	ec/lenovo/h8: Align macro values in one column	2020-07-26 21:40:00 +00:00
include	assert.h: Try to evaluate assertions at compile time	2020-08-03 05:15:59 +00:00
lib	lib/string: Add standard strstr() function	2020-08-03 05:12:23 +00:00
mainboard	nb/intel/ironlake: Drop `D0F0_` prefix from register names	2020-08-03 05:28:57 +00:00
northbridge	nb/intel/ironlake: Correct PCIEXBAR definition	2020-08-03 05:30:59 +00:00
security	security/intel/txt: Add Intel TXT support	2020-07-31 16:02:54 +00:00
soc	src/soc/intel/jasperlake: Update SD card ACPI device	2020-08-03 05:20:52 +00:00
southbridge	Change all assert(0) to BUG()	2020-08-03 05:15:15 +00:00
superio	superio/common: Avoid NULL pointer dereference	2020-07-24 21:21:09 +00:00
vendorcode	vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments	2020-08-02 16:45:22 +00:00
Kconfig	arch/x86: Remove RELOCATABLE_RAMSTAGE	2020-07-06 06:17:47 +00:00