70342a7f51
The port for console remains to be a compile time constant. The Kconfig option is changed to select an UART port with index to avoid putting map of UART base addresses in Kconfigs. With this change it is possible to have other than debug console on different UART port. Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5342 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
125 lines
3.3 KiB
C
125 lines
3.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Eric Biederman
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* Copyright (C) 2006-2010 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/uart.h>
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#include <device/device.h>
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#include <delay.h>
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#include "uart8250reg.h"
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/* Should support 8250, 16450, 16550, 16550A type UARTs */
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/* Expected character delay at 1200bps is 9ms for a working UART
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* and no flow-control. Assume UART as stuck if shift register
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* or FIFO takes more than 50ms per character to appear empty.
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*/
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#define SINGLE_CHAR_TIMEOUT (50 * 1000)
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#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
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static int uart8250_mem_can_tx_byte(unsigned base_port)
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{
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return read8(base_port + UART_LSR) & UART_LSR_THRE;
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}
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static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
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{
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unsigned long int i = SINGLE_CHAR_TIMEOUT;
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while(i-- && !uart8250_mem_can_tx_byte(base_port))
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udelay(1);
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write8(base_port + UART_TBR, data);
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}
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static void uart8250_mem_tx_flush(unsigned base_port)
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{
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unsigned long int i = FIFO_TIMEOUT;
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while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT))
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udelay(1);
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}
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static int uart8250_mem_can_rx_byte(unsigned base_port)
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{
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return read8(base_port + UART_LSR) & UART_LSR_DR;
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}
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static unsigned char uart8250_mem_rx_byte(unsigned base_port)
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{
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unsigned long int i = SINGLE_CHAR_TIMEOUT;
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while(i-- && !uart8250_mem_can_rx_byte(base_port))
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udelay(1);
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if (i)
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return read8(base_port + UART_RBR);
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else
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return 0x0;
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}
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static void uart8250_mem_init(unsigned base_port, unsigned divisor)
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{
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/* Disable interrupts */
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write8(base_port + UART_IER, 0x0);
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/* Enable FIFOs */
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write8(base_port + UART_FCR, UART_FCR_FIFO_EN);
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/* Assert DTR and RTS so the other end is happy */
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write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
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/* DLAB on */
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write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS);
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write8(base_port + UART_DLL, divisor & 0xFF);
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write8(base_port + UART_DLM, (divisor >> 8) & 0xFF);
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/* Set to 3 for 8N1 */
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write8(base_port + UART_LCR, CONFIG_TTYS0_LCS);
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}
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void uart_init(int idx)
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{
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u32 base = uart_platform_base(idx);
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if (!base)
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return;
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unsigned int div;
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div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16);
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uart8250_mem_init(base, div);
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}
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void uart_tx_byte(int idx, unsigned char data)
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{
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u32 base = uart_platform_base(idx);
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if (!base)
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return;
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uart8250_mem_tx_byte(base, data);
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}
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unsigned char uart_rx_byte(int idx)
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{
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u32 base = uart_platform_base(idx);
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if (!base)
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return 0xff;
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return uart8250_mem_rx_byte(base);
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}
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void uart_tx_flush(int idx)
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{
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u32 base = uart_platform_base(idx);
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if (!base)
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return;
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uart8250_mem_tx_flush(base);
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}
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