coreboot-kgpe-d16/src/northbridge
Timothy Pearson db84a99011 nb/amd/mct_ddr3: Properly set MR0 WR value
The existing code accidentally truncated the MSB from the MR0
WR value.  While this probably had a minimal effect in reality,
it should be configured correctly for maximal system stability.

Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13147
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-24 23:26:59 +01:00
..
amd nb/amd/mct_ddr3: Properly set MR0 WR value 2016-01-24 23:26:59 +01:00
dmp/vortex86ex tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
intel nb/intel/pineview: Use macro names for memory base registers 2016-01-20 16:26:22 +01:00
rdc/r8610 tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
via Correct some common spelling mistakes 2016-01-07 22:57:02 +01:00