Werner Zeh 4f7fe494a0 mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge ... On this mainboard variant the PCIe-2-PCI bridge is used a bit different. Adjust the switched off clock lines to match the mainboard configuration. Change-Id: I16f3b6eed0948c8201baecdfbb8052c6c1c335c8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>		2019-11-11 10:34:55 +00:00
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mc_apl1	mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge	2019-11-11 10:34:55 +00:00
mc_bdx1	src: Use 'include <boot/coreboot_tables.h>' when appropriate	2019-10-27 17:48:30 +00:00
mc_tcu3	soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi	2019-11-01 11:50:03 +00:00
Kconfig
Kconfig.name