coreboot-kgpe-d16/src
Yinghai Lu bc7ceb1fd1 Add support for the Winbond W83627EHG Super I/O.
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Bingxun Shi  <bingxunshi@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-03 15:28:20 +00:00
..
arch great check-in message: 2007-02-01 00:44:27 +00:00
boot Apply linuxbios-rename-other-payload-options.patch 2006-12-15 12:56:28 +00:00
config Apply linuxbios-rename-other-payload-options.patch 2006-12-15 12:56:28 +00:00
console make ppc happy for console 2006-10-05 00:27:44 +00:00
cpu Change 'ram' to 'RAM' in user-visible output (closes #60). 2007-01-16 11:56:35 +00:00
devices This change fixes a long-standing bug, whereby we do not set ret for an 2006-10-27 18:22:13 +00:00
drivers Use the canonical name of the vendors/devices and the 2006-11-05 18:50:49 +00:00
include This patch adds the MCP55 PCI IDs (without which the southbridge code 2007-02-01 01:53:55 +00:00
lib replace table based crc with computational one. by Ed Swierk. 2006-10-09 22:35:45 +00:00
mainboard Remove hardcoded gcc versions otherwise the build will break for 2007-02-02 17:08:04 +00:00
northbridge Fix typo which breaks the build ('defalut' should be 'default'). 2007-02-01 22:43:27 +00:00
pc80 implement io based udelay function for all mainboards that lack an apic 2005-12-04 17:50:32 +00:00
pmc/altimus/mpc7410 Use the common LinuxBIOS license header (trivial). Refs #5. 2006-12-05 15:27:46 +00:00
ram - Adds support for the Advantech eval board. Configuration was produced 2006-04-01 04:10:44 +00:00
sdram 1201_ht_bus0_dev0_fidvid_core.diff 2005-12-02 21:52:30 +00:00
southbridge Nvidia MCP55 uses CMD to send/receive bytes instead of DAT0, 2007-02-03 15:23:34 +00:00
stream This eliminates an illegal and annoying warning. 2007-02-03 10:43:48 +00:00
superio Add support for the Winbond W83627EHG Super I/O. 2007-02-03 15:28:20 +00:00