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coreboot-kgpe-d16/src/northbridge/intel
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Sebastian Andrzej Siewior 50dd47bb58 northbridge/sch: Read the GPU memory from the correct PCI device 
The GGC register which contains the size of memory that is used for GPU
is in PCI device 2,0 and not 0,0. It is set to to 4MiB in
src/mainboard/iwave/iWRainbowG6/romstage.c.

Change-Id: Ie9f1cc60544ecd9cad770f34c83c33564a6129d4
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-on: http://review.coreboot.org/1628
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-10-26 21:54:50 +02:00
..
e7501 Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
e7505 Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
e7520 Auto-declare chip_operations 2012-08-22 05:06:41 +02:00
e7525 Auto-declare chip_operations 2012-08-22 05:06:41 +02:00
i440bx Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
i440lx Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
i855 Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
i945 Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
i3100 Auto-declare chip_operations 2012-08-22 05:06:41 +02:00
i5000 Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
i82810 Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
i82830 Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
sandybridge Auto-declare chip_operations 2012-08-22 05:06:41 +02:00
sch northbridge/sch: Read the GPU memory from the correct PCI device 2012-10-26 21:54:50 +02:00
Kconfig Add support for Intel Sandybridge CPU (northbridge part) 2012-04-05 20:59:31 +02:00
Makefile.inc Add support for Intel Sandybridge CPU (northbridge part) 2012-04-05 20:59:31 +02:00