Raul E Rangel e6cd6caf31 cpu/x86/smm: Add weak SoC init and exit methods ... This change provides hooks for the SoC so it can perform any initialization and cleanup in the SMM handler. For example, if we have a UART enabled firmware with DEBUG_SMI, the UART controller could have been powered off by the OS. In this case we need to power on the UART when entering SMM, and then power it off before we exit. If the OS had the UART enabled when entering SMM, we should snapshot the UART register state, and restore it on exit. Otherwise we risk clearing some interrupt enable bits. BUG=b:221231786, b:217968734 TEST=Build test guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I946619cd62a974a98c575a92943b43ea639fc329 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>		2022-03-10 17:06:51 +00:00
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amd	cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic number	2022-02-25 17:44:45 +00:00
armltd	…
intel	cpu/intel/common: Add support for energy performance preference (EPP)	2022-03-09 22:57:04 +00:00
power9	src/cpu/power9: add file structure for power9, implement SCOM access	2022-02-11 13:53:29 +00:00
qemu-power8	…
qemu-x86	cpu/x86/lapic: Move LAPIC configuration to MP init	2022-02-05 07:59:04 +00:00
x86	cpu/x86/smm: Add weak SoC init and exit methods	2022-03-10 17:06:51 +00:00
Kconfig	…
Makefile.inc	src/cpu/power9: add file structure for power9, implement SCOM access	2022-02-11 13:53:29 +00:00