Jacob Garber 715d60abce sb/amd/sr5650: Add fine-grained bounds checking ... The code currently checks that 4 <= dev_index <= 10, which after subtraction by 4 can index into an array of length at most 7. This is fine for the largest cpl array (which does have length 7), but is too large for some of the others, which are smaller. This adds bounds checks for each array access to ensure they are all within bounds. Change-Id: I1610d35ca6cbb6cfb42c251e75b0e8b22b64252b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229676 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2019-07-17 16:06:46 +00:00
..
acpi
chip.h
cmn.h	arch/io.h: Drop unnecessary include	2019-03-04 15:08:03 +00:00
early_setup.c	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	2019-03-08 08:33:24 +00:00
ht.c	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	2019-03-08 08:33:24 +00:00
Kconfig
Makefile.inc
pcie.c	sb/amd/sr5650: Add fine-grained bounds checking	2019-07-17 16:06:46 +00:00
rev.h
sr5650.c	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	2019-03-08 08:33:24 +00:00
sr5650.h	southbridge: Remove useless include <device/pci_ids.h>	2018-12-19 05:23:03 +00:00