Raul E Rangel 5461662c66 soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI ... Required so we pass SPI information down to depthcharge. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2021-02-10 19:01:22 +00:00
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amd	soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI	2021-02-10 19:01:22 +00:00
cavium	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
example	arch/x86: Move prologue to .init section	2021-01-07 11:02:03 +00:00
intel	soc/intel/xeon_sp/include/soc/acpi_asl.h: Convert to ASL 2.0	2021-02-10 18:02:42 +00:00
mediatek	soc/mediatek/mt8192: Use LZ4 compression for MCUs	2021-02-05 09:42:58 +00:00
nvidia	src: Remove useless comments in "includes" lines	2021-02-04 10:18:49 +00:00
qualcomm	soc/qualcomm/sc7180/aop_load_reset.c: Add missing <program_loading.h>	2021-02-04 09:50:41 +00:00
rockchip	drivers: Replace set_vbe_mode_info_valid	2020-12-17 06:21:56 +00:00
samsung	src: Remove unused <boot_device.h>	2021-02-10 07:22:08 +00:00
sifive	cbfs: Enable CBFS mcache on most chipsets	2020-12-02 22:12:10 +00:00
ti	soc/ti/am335x/header.c: Add missing include	2021-02-03 08:55:15 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00