b9d075b0fc
Host FW status 1 (FWSTS1/HFSTS1) register definition is common across SoCs, hence move it to common. Also add below helper function, * wait_cse_sec_override_mode() - Polls ME status for "HECI_OP_MODE_SEC_OVERRIDE". It's a special CSE mode, the mode ensures CSE does not trigger any spi cycles to CSE region. * set_host_ready() - Clears reset state from host CSR. TEST=Verified CSE recover mode on CML RVP & Hatch board Change-Id: Id5c12b7abdb27c38af74ea6ee568b42ec74bcb3c Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> |
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.. | ||
acpi | ||
basecode | ||
block | ||
pch | ||
acpi.h | ||
acpi_wake_source.c | ||
hda_verb.c | ||
hda_verb.h | ||
Kconfig | ||
Makefile.inc | ||
mma.c | ||
mma.h | ||
nhlt.c | ||
reset.c | ||
reset.h | ||
smbios.c | ||
smbios.h | ||
tpm_tis.c | ||
vbt.c | ||
vbt.h |