Arthur Heymans 58a8953793 Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location" ... In the end it does not look like RCBA register offsets are fully compatible over southbridges. This reverts commit d2d2aef6a3. Is squashed with revert of "sb/intel/common: Fix conflicting OIC register definition" 8aaa00401b. Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>		2018-06-21 15:50:16 +00:00
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e7505	nb/intel/e7505: Leave ROM as un-cacheable in postcar	2018-06-20 19:00:07 +00:00
fsp_rangeley	nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xce	2018-06-14 10:00:03 +00:00
fsp_sandybridge	src: Use "foo *bar" instead of "foo* bar"	2018-06-04 08:52:13 +00:00
gm45	libgfxinit: Enable G45 support (for GM45/X4X)	2018-06-08 03:27:37 +00:00
haswell	cpu/intel/haswell: Use the common intel romstage_main function	2018-06-14 10:01:35 +00:00
i440bx	nb/intel/i440bx: Switch to POSTCAR_STAGE	2018-06-17 19:17:11 +00:00
i945	nb/intel/i945: Enable and allocate 8M for TSEG	2018-06-07 06:41:47 +00:00
nehalem	Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"	2018-06-21 15:50:16 +00:00
pineview	nb/intel/pineview: Enable and allocate 8M for TSEG	2018-06-07 06:42:14 +00:00
sandybridge	Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"	2018-06-21 15:50:16 +00:00
x4x	nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset	2018-06-17 14:17:31 +00:00