coreboot-kgpe-d16/src/soc/amd/stoneyridge
Raul E Rangel 59d64f06be soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume
According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardware_Specification.html#pm1-event-grouping

> For ACPI/legacy systems, when transitioning from the legacy to the G0
> working state this register is cleared by platform firmware prior to
> setting the SCI_EN bit (and thus passing control to OSPM). For ACPI
> only platforms (where SCI_EN is always set), when transitioning from
> either the mechanical off (G3) or soft-off state to the G0 working
> state this register is cleared prior to entering the G0 working state.

This means we don't want to clear the PM1 register on resume. By
clearing it the linux kernel can't correctly increment the wake count
when the power button is pressed. The AMD platforms implement the _SWS
ACPI methods, but the linux kernel doesn't actually use these methods.

BUG=b:172021431
TEST=suspend zork and push power button and verify power button
wake_count increments. Verified other wake sources still work.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-08 20:25:33 +00:00
..
acpi soc/amd/stoneyridge/include/iomap: rename I2C[ABCD]_BASE_ADDRESS defines 2021-10-16 17:55:47 +00:00
include/soc soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 2021-11-30 21:56:00 +00:00
acpi.c soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_ACPI_GPIO 2021-11-25 11:08:36 +00:00
BiosCallOuts.c
bootblock.c soc/amd/common/block/include/i2c: introduce I2C_RESET_SCL_PIN macro 2021-09-09 14:20:35 +00:00
chip.c cpu/amd/mtrr: Remove topmem global variables 2021-11-03 18:36:15 +00:00
chip.h src/soc to src/superio: Fix spelling errors 2021-10-05 18:07:08 +00:00
cpu.c soc/amd/*/cpu: handle mp_init_with_smm failure 2021-11-03 18:37:28 +00:00
enable_usbdebug.c
fw_cz.cfg soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION 2020-11-04 09:42:18 +00:00
fw_st.cfg soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION 2020-11-04 09:42:18 +00:00
gpio.c soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h 2021-09-23 18:33:00 +00:00
i2c.c amd/i2c: Remove the weak function 2021-11-04 10:31:37 +00:00
Kconfig soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_ACPI_GPIO 2021-11-25 11:08:36 +00:00
Makefile.inc amdfwtool: Call the set_efs_table for Stoneyridge 2021-11-18 23:29:48 +00:00
mca.c soc/amd/stoneyridge/mca: implement and use mca_has_expected_bank_count 2021-07-15 17:04:28 +00:00
memmap.c soc/amd: fully commonize clear_tvalid 2021-02-11 02:49:34 +00:00
monotonic_timer.c
northbridge.c cpu/amd/mtrr: Remove topmem global variables 2021-11-03 18:36:15 +00:00
psp.c soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1 2021-11-30 21:56:00 +00:00
reset.c soc/amd/stoneyridge/reset: use port and bit defines from cf9_reset.h 2020-12-10 16:00:55 +00:00
romstage.c soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume 2021-12-08 20:25:33 +00:00
sata.c
smbus_spd.c soc/amd/common: Refactor SMBus base arguments 2020-12-15 18:50:13 +00:00
smihandler.c soc/amd/{cezanne,picasso,stoney}: Clear PM/GPE when enabling ACPI 2021-12-08 17:52:03 +00:00
southbridge.c soc/amd/stoneyridge/southbridge: drop ENV_X86 check 2021-12-08 17:53:21 +00:00
tsc_freq.c
uart.c soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_UART 2021-01-14 15:00:55 +00:00
usb.c