Arthur Heymans 19e7273ec2 cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup ... Pineview CPUs support a non-eviction mode that ought to be used during cache as ram setup. This assumes that all atoms that need to set a special register to enable L2 cache are socketed and hence uses a static Kconfig option to set that MSR on affected CPUs. Tested on Foxconn D41S, still boots. Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30863 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-01-15 11:38:01 +00:00
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core2	cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK	2019-01-08 15:33:47 +00:00
non-evict	cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup	2019-01-15 11:38:01 +00:00
p3	cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK	2019-01-08 15:33:47 +00:00
p4-netburst	arch/x86: Drop Kconfig AP_SIPI_VECTOR	2019-01-13 08:37:01 +00:00
bootblock.c	cpu/intel/car/bootblock.c: Report BIST failures	2019-01-08 15:37:18 +00:00
bootblock.h	cpu/intel/car: Enable use of C_ENVIRONMENT_BOOTBLOCK	2019-01-08 15:35:08 +00:00
romstage.c	cpu/intel: Use the common code to initialize the romstage timestamps	2019-01-09 09:56:06 +00:00