Arthur Heymans 5cb24d4522 soc/intel/cache_as_ram.S: Fix CAR issues with Bootguard ... It looks like the 'clear_car' code does not properly fill the required cachelines so add code to fill cachelines explicitly. Change-Id: Id5d77295f6d24f9d2bc23f39f8772fd172ac8910 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christopher Meis <christopher.meis@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2021-06-26 10:06:23 +00:00
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amd	soc/amd/common/acp: Populate _WOV ACPI method	2021-06-23 19:19:19 +00:00
cavium
example
intel	soc/intel/cache_as_ram.S: Fix CAR issues with Bootguard	2021-06-26 10:06:23 +00:00
mediatek	soc/mediatek/mt8195: Support 4 channel DRAM in DPM init flow	2021-06-24 03:13:53 +00:00
nvidia	cbfs: Replace more instances of cbfs_boot_locate() with newer APIs	2021-03-17 08:10:20 +00:00
qualcomm	sc7280: Add target specific GPIO pin definitions	2021-06-11 07:36:16 +00:00
rockchip	soc/rockchip/rk3399/sdram: Add channel to error message	2021-03-04 01:22:10 +00:00
samsung	commonlib/region: Turn addrspace_32bit into a more official API	2021-04-21 02:06:26 +00:00
sifive	memlayout: Store region sizes as separate symbols	2021-02-19 08:39:26 +00:00
ti	soc/ti/am335x/mmc.c: Fix memset length argument	2021-04-04 09:58:26 +00:00
ucb