Michael Niewöhner 5df952bc2b soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ... Currently, the ACPI PM timer state gets set in devicetree by the option PmTimerDisabled. However, it is not board design dependent. Thus, add a user-selectable Kconfig option. Disabling the PM ACPI Timer is only valid when PM Timer emulation is supported and is only possible, when there is a hardware PM Timer (APL does not have one for example). SoCs, where the hardware PM Timer can be disabled must select `PM_ACPI_TIMER_OPTIONAL`. This new Kconfig gets used in the follow-up commits of this series. Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>		2020-11-13 17:18:08 +00:00
..
alderlake	soc/intel/alderlake: Add PCH ID 0x5181	2020-11-12 03:51:49 +00:00
apollolake	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
baytrail	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
braswell	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
broadwell	soc/intel/broadwell: Split up acpi.c	2020-11-13 13:26:02 +00:00
cannonlake	soc/intel/*/chip: Remove unused devicetree entry	2020-11-09 07:27:38 +00:00
common	soc/intel/common: add Kconfig to enable/disable the ACPI PM timer	2020-11-13 17:18:08 +00:00
denverton_ns	soc/intel/denverton_ns: Add PCH_DEVFN_PMC for finding PMC device	2020-11-02 06:28:50 +00:00
elkhartlake	soc/intel/*/chip: Remove unused devicetree entry	2020-11-09 07:27:38 +00:00
icelake	soc/intel/*/chip: Remove unused devicetree entry	2020-11-09 07:27:38 +00:00
jasperlake	soc/intel/jasperlake: Log PM event from an internal device	2020-11-10 06:20:04 +00:00
quark	arch/x86: Introduce ARCH_ALL_STAGES_X86_32	2020-09-26 11:42:28 +00:00
skylake	soc/intel/skylake: Enable PCH thermal depending on devicetree	2020-11-09 21:34:42 +00:00
tigerlake	mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS	2020-11-11 20:44:31 +00:00
xeon_sp	soc/intel/xeon_sp: Tidy up adding MADT ioapic entries	2020-11-13 00:24:46 +00:00
Kconfig