bbac5ace53
memmap.c functionality is designed to be used in more than ramstage. Therefore, it cannot use ramstage-specific APIs. In this case, the SIMPLE_DEVICE API offers a more consistent behavior across stages. Change-Id: Ic381fe1eb773fb0a5fb5887eb67d2228d2f0817d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14953 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* The device_t returned by dev_find_slot() is different than the device_t
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* passed to pci_write_config32(). If one needs to get access to the config.h
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* of a device and perform i/o things are incorrect. One is a pointer while
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* the other is a 32-bit integer.
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*/
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#define __SIMPLE_DEVICE__
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#include <arch/io.h>
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#include <cbmem.h>
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#include <device/pci.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <soc/smm.h>
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static uintptr_t smm_region_start(void)
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{
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return ALIGN_DOWN(pci_read_config32(NB_DEV_ROOT, TSEG), 1*MiB);
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}
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static size_t smm_region_size(void)
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{
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uintptr_t smm_end =
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ALIGN_DOWN(pci_read_config32(NB_DEV_ROOT, BGSM), 1*MiB);
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return smm_end - smm_region_start();
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}
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void *cbmem_top(void)
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{
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return (void *)smm_region_start();
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}
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void smm_region(void **start, size_t *size)
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{
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*start = (void *)smm_region_start();
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*size = smm_region_size();
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}
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