aa902036d0
The wake source macro for GPE events was using 'GPIO'. However, current usage is really all GPEs. Therefore, provide clarity in the naming in order to allow for proper GPIO wake events that are separate from the ACPI GPE block. BUG=b:159947207 Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
89 lines
2.1 KiB
C
89 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <elog.h>
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#include <soc/iomap.h>
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#include <soc/pm.h>
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#include <stdint.h>
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static void log_power_and_resets(const struct chipset_power_state *ps)
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{
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if (ps->gen_pmcon1 & PWR_FLR) {
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elog_add_event(ELOG_TYPE_POWER_FAIL);
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elog_add_event(ELOG_TYPE_PWROK_FAIL);
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}
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if (ps->gen_pmcon1 & SUS_PWR_FLR)
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elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
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if (ps->gen_pmcon1 & RPS)
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elog_add_event(ELOG_TYPE_RTC_RESET);
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if (ps->tco_sts & SECOND_TO_STS)
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elog_add_event(ELOG_TYPE_TCO_RESET);
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if (ps->pm1_sts & PRBTNOR_STS)
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elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
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if (ps->gen_pmcon1 & SRS)
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elog_add_event(ELOG_TYPE_RESET_BUTTON);
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if (ps->gen_pmcon1 & GEN_RST_STS)
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elog_add_event(ELOG_TYPE_SYSTEM_RESET);
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}
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static void log_wake_events(const struct chipset_power_state *ps)
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{
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const uint32_t pcie_wake_mask = PCIE_WAKE3_STS | PCIE_WAKE2_STS |
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PCIE_WAKE1_STS | PCIE_WAKE0_STS | PCI_EXP_STS;
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uint32_t gpe0_sts;
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uint32_t gpio_mask;
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int i;
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/* Mask off disabled events. */
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gpe0_sts = ps->gpe0_sts & ps->gpe0_en;
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if (ps->pm1_sts & WAK_STS)
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elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
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acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5);
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if (ps->pm1_sts & PWRBTN_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
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if (ps->pm1_sts & RTC_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
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if (gpe0_sts & PME_B0_EN)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
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if (gpe0_sts & pcie_wake_mask)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
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gpio_mask = SUS_GPIO_STS0;
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i = 0;
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while (gpio_mask) {
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if (gpio_mask & gpe0_sts)
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elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i);
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gpio_mask <<= 1;
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i++;
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}
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}
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void southcluster_log_state(void)
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{
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struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
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if (ps == NULL) {
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printk(BIOS_DEBUG,
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"Not logging power state information. Power state not found in cbmem.\n");
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return;
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}
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log_power_and_resets(ps);
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log_wake_events(ps);
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}
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