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coreboot-kgpe-d16/src
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Aaron Durbin 6d04f0f89e haswell: always use MMIO PCI config accesses 
Add a bootblock.c file for the northbridge and setup the
PCIEXBAR as the first thing using IO PCI config acceses.
After that all PCI config accesses can use MMIO.

Change-Id: I51d229c626c45705dda1757c2f14265cbc0e6183
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2617
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
 		2013-03-14 01:45:50 +01:00
..
arch Eliminate do_div(). 2013-03-08 23:14:26 +01:00
console Eliminate do_div(). 2013-03-08 23:14:26 +01:00
cpu haswell: Add initial support for Haswell platforms 2013-03-14 01:44:40 +01:00
device GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
drivers GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
ec GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
include watchdog.h: Fix compile time error on disabling watchdog handling 2013-03-12 12:06:43 +01:00
lib Eliminate do_div(). 2013-03-08 23:14:26 +01:00
mainboard Eagleheights DSDT: Grant OS control through OSC 2013-03-13 23:44:00 +01:00
northbridge haswell: always use MMIO PCI config accesses 2013-03-14 01:45:50 +01:00
southbridge haswell: Add initial support for Haswell platforms 2013-03-14 01:44:40 +01:00
superio AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio 2013-03-06 19:07:28 +01:00
vendorcode AGESA: Fix CR0_PE bit define 2013-03-08 07:30:06 +01:00
Kconfig bump SeaBIOS to 1.7.2.1 2013-03-04 11:00:17 +01:00