Patrick Georgi 803cf02801 mainboards: Add SMMSTORE region in chromeos configs ... Only for those that are x86 and also have a RW_LEGACY region. The assumption is that all devices touched have 64k block sizes when choosing size and alignment of the region. Change-Id: I12addb137604f003d1296f34f555dae219330b18 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2018-09-12 12:25:30 +00:00
..
spd	mainboard/google/zoombini: consolidate SPD makefiles	2018-02-28 17:38:47 +00:00
variants	soc/intel/cannonlake: Change LPDDR4 to MEMCFG	2018-08-28 15:15:26 +00:00
acpi_tables.c
board_info.txt
boardid.c	boardid: Minor clean up and standardization	2017-12-07 01:18:25 +00:00
bootblock.c
chromeos.c	mb/google/zoombini: always report EC is in RO mode	2018-03-23 08:54:59 +00:00
chromeos.fmd	mainboards: Add SMMSTORE region in chromeos configs	2018-09-12 12:25:30 +00:00
dsdt.asl	mb/google/x86-boards: Get rid of power button device in coreboot	2018-07-25 18:52:40 +00:00
ec.c	ec/google/chromeec: Add library function google_chromeec_events_init	2017-10-08 19:38:28 +00:00
Kconfig	soc/intel/cannonlake: Change LPDDR4 to MEMCFG	2018-08-28 15:15:26 +00:00
Kconfig.name	mainboard/google: Comment variant names in Kconfig	2018-05-04 01:03:49 +00:00
mainboard.c	mb/google: Get rid of device_t	2018-05-08 18:31:26 +00:00
Makefile.inc	mainboard/google/zoombini: consolidate SPD makefiles	2018-02-28 17:38:47 +00:00
memory.c	soc/intel/cannonlake: Change LPDDR4 to MEMCFG	2018-08-28 15:15:26 +00:00
ramstage.c	mainboard/google/zoombini: add gpio init to ramstage	2018-01-11 01:10:01 +00:00
romstage.c	soc/intel/cannonlake: Change LPDDR4 to MEMCFG	2018-08-28 15:15:26 +00:00
smihandler.c