6c2568f4f5
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability. BUG=b:150502246 BRANCH=None TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled). Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> |
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.. | ||
acpi | ||
bootblock | ||
include/soc | ||
acpi.c | ||
chip.c | ||
chip.h | ||
cpu.c | ||
csme_ie_kt.c | ||
fiamux.c | ||
gpio.c | ||
gpio_dnv.c | ||
hob_display.c | ||
hob_mem.c | ||
Kconfig | ||
lpc.c | ||
Makefile.inc | ||
memmap.c | ||
npk.c | ||
pmc.c | ||
pmutil.c | ||
reset.c | ||
romstage.c | ||
sata.c | ||
smihandler.c | ||
smm.c | ||
soc_util.c | ||
spi.c | ||
systemagent.c | ||
tsc_freq.c | ||
uart.c | ||
uart_debug.c | ||
upd_display.c | ||
xhci.c |