coreboot-kgpe-d16/src/mainboard/intel/cannonlake_rvp
Subrata Banik 1ed36f9ce9 mainboard/intel: Update mainboard UART Kconfig
After a96e66a (soc/intel: Clean mess around UART_DEBUG) got merged,
all mainboard using intel cannonlake,coffeelake, kabylake, skylake,
icelake and whiskeylake get affected.

Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.

TEST=Intel client and IoT team has verified that LPSS uart
is working fine on CNL, WHL and ICL RVPs.

Change-Id: I0381a6616f03c74c98f837e3c008459fefd4818c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30913
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 16:26:56 +00:00
..
spd src: Remove unneeded include <cbfs.h> 2018-11-16 10:26:32 +00:00
variants mb/cannonlake: Remove SmbusEnable from devicetree 2018-11-13 16:32:27 +00:00
acpi_tables.c
board_info.txt
bootblock.c
chromeos.c buildsystem: Promote rules.h to default include 2019-01-16 11:51:07 +00:00
chromeos.fmd mainboards: Add SMMSTORE region in chromeos configs 2018-09-12 12:25:30 +00:00
dsdt.asl mb: Set coreboot as DSDT's manufacturer model ID 2018-11-23 11:00:40 +00:00
Kconfig mainboard/intel: Update mainboard UART Kconfig 2019-01-16 16:26:56 +00:00
Kconfig.name intel/cannonlake_rvp: Update board name 2017-10-20 20:52:50 +00:00
mainboard.c mainboard: Get rid of device_t in ramstage 2018-06-09 16:39:35 +00:00
Makefile.inc mb/intel/cannonlake_rvp: Move FSP param override function to separate file 2018-10-04 09:47:22 +00:00
romstage_fsp_params.c mb/intel/cannonlake_rvp: Move FSP param override function to separate file 2018-10-04 09:47:22 +00:00
smihandler.c