coreboot-kgpe-d16/src/soc/intel/tigerlake
Jes Klinke 6fd87ffe2e soc/intel/tigerlake: Allow fine grained control of S0iX states
Expose devicetree parameter to enable/disable each individual substate.

See https://review.coreboot.org/c/coreboot/+/43741 for context.

TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
BUG=b:154333137

Change-Id: I8a0cf820e20961486813067c6945fe07bc4899f7
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44355
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:11:19 +00:00
..
acpi src: Remove extra lines in license header 2020-07-26 20:57:18 +00:00
bootblock soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE 2020-08-07 06:05:12 +00:00
include/soc soc/intel/tigerlake: Add IRQs for LPSS uart 2020-08-12 05:30:28 +00:00
romstage soc/intel/tigerlake: Simplify is-device-enabled checks 2020-07-28 08:36:59 +00:00
spd/lp4x lp4x: Add new memory parts and generate SPDs 2020-07-07 04:18:55 +00:00
acpi.c soc/intel/tigerlake: Simplify is-device-enabled checks 2020-07-28 08:36:59 +00:00
chip.c soc/intel/tigerlake: Invoke PCIe root port swapping 2020-08-03 05:06:34 +00:00
chip.h soc/intel/tigerlake: Allow fine grained control of S0iX states 2020-08-17 07:11:19 +00:00
cpu.c soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming 2020-08-09 11:03:37 +00:00
elog.c src: Remove unused 'include <cbmem.h>' 2020-07-26 20:59:44 +00:00
espi.c soc/intel: Drop unused #include <reg_script.h> 2020-07-06 19:29:07 +00:00
finalize.c soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus master 2020-07-07 17:29:56 +00:00
fsp_params.c soc/intel/tigerlake: Allow fine grained control of S0iX states 2020-08-17 07:11:19 +00:00
gpio.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
gspi.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
i2c.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
Kconfig soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 5KB 2020-08-14 23:06:08 +00:00
lockdown.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
Makefile.inc soc/intel/gma: Implement fsp_soc_get_igd_bar() in common code 2020-05-27 21:35:43 +00:00
me.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
meminit.c soc/intel/tigerlake: add common routine for DDR init 2020-08-06 17:42:20 +00:00
p2sb.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
pmc.c drivers/intel/pmx_mux: Remove redundant declaration 2020-07-03 08:28:20 +00:00
pmutil.c soc/intel/tigerlake: Move pmc_soc_set_afterg3_en to pmutil 2020-05-20 09:49:26 +00:00
reset.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
smihandler.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
smmrelocate.c soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming 2020-08-09 11:03:37 +00:00
soundwire.c soc/intel/tigerlake: Provide SoundWire controller properties 2020-05-22 01:48:39 +00:00
spi.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
systemagent.c soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU 2020-07-25 00:07:36 +00:00
uart.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00