coreboot-kgpe-d16/src/superio
Edward O'Callaghan bf9f243857 superio/common/conf_mode: Provide another common pnp entry/exit
ITE Super I/O's make use of this method to enter and exit in and out of
their PNP configuration. Provide functions for use in ram stage
component.

Change-Id: I2b546c2b17eefc89aaab4982192f5e9a15a16c2f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5666
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-07 21:36:48 +02:00
..
acpi winbond/w83627dhg: Fix logical device power down in ACPI 2013-07-03 17:58:20 +02:00
common superio/common/conf_mode: Provide another common pnp entry/exit 2014-05-07 21:36:48 +02:00
fintek superio/fintek/*: Factor out generic romstage component 2014-04-26 18:22:11 +02:00
intel uart8250: Drop includes in superio 2014-02-06 11:17:24 +01:00
ite superio/ite/it8673f: Remove poor implementation 2014-04-26 13:10:54 +02:00
nsc uart8250: Drop includes in superio 2014-02-06 11:17:24 +01:00
nuvoton superio/nuvoton/nct5104d: Avoid .c includes 2014-04-06 06:08:37 +02:00
renesas uart8250: Drop includes in superio 2014-02-06 11:17:24 +01:00
serverengines x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
smsc uart8250: Drop includes in superio 2014-02-06 11:17:24 +01:00
via uart: Redefine Kconfig options 2014-04-09 11:24:43 +02:00
winbond superio/winbond/w83627thg: Remove w83627thg_enable_serial symbol 2014-05-02 09:44:58 +02:00
Kconfig AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio 2013-03-06 19:07:28 +01:00
Makefile.inc Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00