508dc163f1
Move PMC EPOC related code to intel/common/block because it is generic for most Intel platforms and ADL, TGL & EHL use it. Add a kconfig 'PMC_EPOC' to guard this common EPOC code. The PMC EPOC register indicates which external crystal oscillator is connected to the PCH. This frequency is important for determining the IP clock of internal PCH devices. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ib5fd3c4a648964678ee40ed0f60ca10fe7953f56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
71 lines
1.9 KiB
C
71 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_soundwire.h>
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/soundwire.h>
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#include <drivers/intel/soundwire/soundwire.h>
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#include <intelblocks/pmclib.h>
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#include <stddef.h>
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#include <string.h>
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static const struct soundwire_link link_xtal_38_4 = {
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.clock_stop_mode0_supported = 1,
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.clock_stop_mode1_supported = 1,
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.clock_frequencies_supported_count = 1,
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.clock_frequencies_supported = { 4800 * KHz },
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.default_frame_rate = 48 * KHz,
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.default_frame_row_size = 50,
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.default_frame_col_size = 4,
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.dynamic_frame_shape = 1,
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.command_error_threshold = 16,
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};
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static const struct soundwire_link link_xtal_24 = {
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.clock_stop_mode0_supported = 1,
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.clock_stop_mode1_supported = 1,
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.clock_frequencies_supported_count = 1,
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.clock_frequencies_supported = { 6 * MHz },
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.default_frame_rate = 48 * KHz,
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.default_frame_row_size = 125,
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.default_frame_col_size = 2,
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.dynamic_frame_shape = 1,
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.command_error_threshold = 16,
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};
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static struct intel_soundwire_controller intel_controller = {
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.acpi_address = 0x40000000,
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.sdw = {
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.master_list_count = 4
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}
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};
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int soc_fill_soundwire_controller(struct intel_soundwire_controller **controller)
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{
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const struct soundwire_link *link;
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enum pch_pmc_xtal xtal = pmc_get_xtal_freq();
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size_t i;
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/* Select link config based on XTAL frequency and set IP clock. */
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switch (xtal) {
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case XTAL_24_MHZ:
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link = &link_xtal_24;
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intel_controller.ip_clock = 24 * MHz;
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break;
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case XTAL_38_4_MHZ:
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link = &link_xtal_38_4;
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intel_controller.ip_clock = 38400 * KHz;
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break;
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case XTAL_19_2_MHZ:
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default:
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printk(BIOS_ERR, "%s: XTAL not supported: 0x%x\n", __func__, xtal);
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return -1;
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}
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/* Fill link config in controller map based on selected XTAL. */
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for (i = 0; i < intel_controller.sdw.master_list_count; i++)
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memcpy(&intel_controller.sdw.master_list[i], link, sizeof(*link));
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*controller = &intel_controller;
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return 0;
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}
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