Tim Wawrzynczak 26e384bf34 soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0 ... The macro was defined using PCH_DEV_SLOT_CPU_1, which doesn't exist, so replace it with the correct value of SA_DEV_SLOT_CPU_1. Change-Id: If6d294d681907c51ac5678c9251364d4d6df4329 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>		2021-12-09 20:52:43 +00:00
..
acpi	Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"	2021-11-17 15:54:10 +00:00
bootblock	soc/intel/common: Include Alder Lake-N device IDs	2021-11-29 09:46:40 +00:00
include/soc	soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0	2021-12-09 20:52:43 +00:00
romstage	soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.h	2021-12-06 12:31:09 +00:00
acpi.c	soc/intel: Constify soc_get_cstate_map()	2021-10-19 14:57:59 +00:00
chip.c	soc/intel/alderlake: Add igd device	2021-09-16 00:05:21 +00:00
chip.h	soc/intel/alderlake: Add the CnviDdrRfim configuration	2021-12-03 15:48:27 +00:00
chipset.cb	soc/intel/alderlake: Add ADLP 4+4+2 power configurations	2021-11-25 19:43:00 +00:00
cpu.c	soc/intel/alderlake: Add support for ADL-N CPU Type	2021-12-06 12:39:47 +00:00
crashlog.c	soc/intel/alderlake: remove tmp bar assignment for cpu crashlog	2021-11-23 09:21:16 +00:00
dptf.c	drivers/intel/dptf: Add support for PCH methods	2021-10-11 12:45:47 +00:00
elog.c	soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros	2021-05-03 16:28:53 +00:00
espi.c	src: Match array format in function declarations and definitions	2021-05-13 18:34:38 +00:00
finalize.c	soc/intel/{adl,ehl,jsl,tgl}: Remove unused header thermal.h	2021-11-22 08:02:48 +00:00
fsp_params.c	soc/intel/alderlake: Add TDP to give correct VR configuration	2021-12-03 15:37:44 +00:00
gpio.c	soc/intel/alderlake: enable gpio locking	2021-12-07 00:17:45 +00:00
gspi.c
i2c.c	soc/intel/alderlake: Add support for I2C6 and I2C7	2021-07-20 13:35:10 +00:00
Kconfig	soc/intel/alderlake: enable gpio locking	2021-12-07 00:17:45 +00:00
lockdown.c
Makefile.inc	soc/intel/alderlake: Fix build failure with enabled CSE stitching	2021-11-15 23:02:55 +00:00
me.c
meminit.c	soc/intel/alderlake: Implement WA for DDR5 DIMM modules	2021-07-13 14:30:07 +00:00
p2sb.c
pcie_rp.c
pmc.c	soc/intel: implement ACPI timer disabling per SoC and drop common code	2021-10-17 13:57:53 +00:00
pmutil.c
reset.c
smihandler.c	soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster	2021-05-07 06:05:18 +00:00
soundwire.c	soc/intel/common: Move PMC EPOC related code to Intel common code	2021-06-30 07:34:44 +00:00
spi.c	soc/intel: Update api name for getting spi destination id	2021-10-26 18:12:17 +00:00
systemagent.c	Rename ECAM-specific MMCONF Kconfigs	2021-11-10 17:24:16 +00:00
uart.c	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
vr_config.c	soc/intel/alderlake: Add ADL-P 6+8+2 (28W) VR config	2021-12-06 16:39:57 +00:00
xhci.c	soc/intel/alderlake: Correct TCSS XHCI Port status offset	2021-06-08 15:25:29 +00:00