1f8563ec0e
We only have ADL-P 6+8+2 (45W) VR configuration now. Based on the power map, fill in correct ADL-P 6+8+2 (28W) VR configuration. BUG=b:202486131 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: Ie8dbd95b2d8e49b5898b2a97aff72e0e64868c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
139 lines
6 KiB
C
139 lines
6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <fsp/api.h>
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#include <soc/ramstage.h>
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#include <soc/vr_config.h>
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#include <console/console.h>
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#include <intelblocks/cpulib.h>
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/*
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* VR Configurations for IA and GT domains for ADL-P SKU's.
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* Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation
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* for ADL-P 482(28W) and 442(45W).
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*
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* +----------------+-----------+-------+-------+---------+-------------+----------+
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* | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
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* | | |(mOhms)|(mOhms)| (A) | (A) | (msec) |
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* +----------------+-----------+-------+-------+---------+-------------+----------+
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* | ADL-P 682(45W) | IA | 2.3 | 2.3 | 160 | 57 | 28000 |
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* + +-----------+-------+-------+---------+-------------+----------+
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* | | GT | 3.2 | 3.2 | 50 | 57 | 28000 |
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* +----------------+-----------+-------+-------+---------+-------------+----------+
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* | ADL-P 482(28W) | IA | 2.3 | 2.3 | 85 | 40 | 28000 |
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* + +-----------+-------+-------+---------+-------------+----------+
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* | | GT | 3.2 | 3.2 | 50 | 40 | 28000 |
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* +----------------+-----------+-------+-------+---------+-------------+----------+
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* | ADL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 20 | 28000 |
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* + +-----------+-------+-------+---------+-------------+----------+
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* | | GT | 3.2 | 3.2 | 40 | 20 | 28000 |
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* +----------------+-----------+-------+-------+---------+-------------+----------+
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*/
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struct vr_lookup {
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uint16_t mchid;
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uint8_t tdp;
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uint32_t conf[NUM_VR_DOMAINS];
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};
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static uint32_t load_table(const struct vr_lookup *tbl, const int tbl_entries, const int domain,
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const uint16_t mch_id, uint8_t tdp)
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{
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for (size_t i = 0; i < tbl_entries; i++) {
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if (tbl[i].mchid != mch_id || tbl[i].tdp != tdp)
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continue;
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return tbl[i].conf[domain];
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}
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printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in %s\n", mch_id, __func__);
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return 0;
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}
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/* Per the power map from #613643, update ADL-P 6+8+2 (28W) VR configuration */
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static const struct vr_lookup vr_config_ll[] = {
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
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};
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static const struct vr_lookup vr_config_icc[] = {
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 50) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 50) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(111, 50) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 50) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
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};
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static const struct vr_lookup vr_config_tdc_timewindow[] = {
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
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};
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static const struct vr_lookup vr_config_tdc_currentlimit[] = {
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
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{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
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};
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void fill_vr_domain_config(FSP_S_CONFIG *s_cfg,
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int domain, const struct vr_config *chip_cfg)
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{
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const struct vr_config *cfg;
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if (domain < 0 || domain >= NUM_VR_DOMAINS)
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return;
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/* Use device tree override if requested */
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if (chip_cfg->vr_config_enable) {
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cfg = chip_cfg;
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if (cfg->ac_loadline)
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s_cfg->AcLoadline[domain] = cfg->ac_loadline;
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if (cfg->dc_loadline)
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s_cfg->DcLoadline[domain] = cfg->dc_loadline;
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if (cfg->icc_max)
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s_cfg->IccMax[domain] = cfg->icc_max;
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s_cfg->TdcTimeWindow[domain] = cfg->tdc_timewindow;
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s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit;
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} else {
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uint16_t mch_id = 0;
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uint8_t tdp = get_cpu_tdp();
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if (!mch_id) {
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struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
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mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
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}
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s_cfg->AcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll),
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domain, mch_id, tdp);
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s_cfg->DcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll),
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domain, mch_id, tdp);
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s_cfg->IccMax[domain] = load_table(vr_config_icc, ARRAY_SIZE(vr_config_icc),
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domain, mch_id, tdp);
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s_cfg->TdcTimeWindow[domain] = load_table(vr_config_tdc_timewindow,
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ARRAY_SIZE(vr_config_tdc_timewindow),
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domain, mch_id, tdp);
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s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit,
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ARRAY_SIZE(vr_config_tdc_currentlimit),
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domain, mch_id, tdp);
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}
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/* Check TdcTimeWindow and TdcCurrentLimit,
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Set TdcEnable and Set VR TDC Input current to root mean square */
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if (s_cfg->TdcTimeWindow[domain] != 0 && s_cfg->TdcCurrentLimit[domain] != 0) {
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s_cfg->TdcEnable[domain] = 1;
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s_cfg->Irms[domain] = 1;
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}
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}
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