coreboot-kgpe-d16/src
Alexandru Gagniuc 717dccc3ee soc/apollolake: Handle non-standard ACPI BAR in PMC device
The ACPI BAR (BAR2 - offset 0x20) is not PCI compliant. That means
that probing may not work. In that case, a resource still needs to be
created for the BAR.

BONUS: We now avoid the need to declare the MMIO resources as fixed.

Change-Id: I52fd2d2718ac8013067aaa450c5eb31e00738ab9
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14634
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-12 04:54:30 +02:00
..
acpi acpi/: add missing license header 2016-01-14 22:52:11 +01:00
arch arch/arm64: add FRAMEBUFFER region macros to memlayout 2016-05-10 23:47:57 +02:00
commonlib cbfstool/fsp: Rename fsp1_1_relocate 2016-05-11 18:38:28 +02:00
console arch/x86: introduce postcar stage/phase 2016-03-23 14:24:30 +01:00
cpu drivers/uart: Use uart_platform_refclk for all UART models 2016-05-09 18:45:44 +02:00
device payloads: add iPXE 'payload' build 2016-04-13 17:45:37 +02:00
drivers drivers/intel/fsp2_0: Add timestamps around all calls to the blob 2016-05-12 04:53:11 +02:00
ec ec/google/chromeec: provide way to query ioport range 2016-05-11 21:33:17 +02:00
include drivers/uart: Enable override for input clock divider 2016-05-09 18:44:47 +02:00
lib lib: remove FLASHMAP_OFFSET config variable 2016-05-11 21:32:44 +02:00
mainboard intel/amenia: Enable touchscreen in ACPI 2016-05-12 04:01:36 +02:00
northbridge nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structure 2016-05-09 20:44:11 +02:00
soc soc/apollolake: Handle non-standard ACPI BAR in PMC device 2016-05-12 04:54:30 +02:00
southbridge drivers/uart: Use uart_platform_refclk for all UART models 2016-05-09 18:45:44 +02:00
superio superio/smsc/mec1308: Fix AddressMax value for SMBX mailbox 2016-04-13 23:39:28 +02:00
vendorcode AGESA boards: Relocate platform memory config 2016-05-10 13:47:08 +02:00
Kconfig lib: remove FLASHMAP_OFFSET config variable 2016-05-11 21:32:44 +02:00