a0199d8e1a
This patch updates the coreboot DDR Settings to match the configuration used by ARM-Trusted-Firmware. Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/20304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> |
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.. | ||
include/soc | ||
bl31_plat_params.c | ||
bootblock.c | ||
chip.h | ||
clock.c | ||
display.c | ||
gpio.c | ||
Kconfig | ||
Makefile.inc | ||
mipi.c | ||
mmu_operations.c | ||
saradc.c | ||
sdram.c | ||
soc.c | ||
timer.c | ||
tsadc.c | ||
usb.c |