coreboot-kgpe-d16/src/soc
Mario Scheithauer e27c096b7f siemens/mc_apl1: Correct the Tx signal from SATA interface
Because of an incorrect transmit voltage swing, the signal must be
adjusted. The factor of slices for full swing level can be corrected via
the High Speed I/O Transmit Control Register 3.

Change-Id: I116802cd2a944658fc3022e948eba43cebe52bb4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2018-08-31 04:11:43 +00:00
..
amd soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port() 2018-08-30 14:47:52 +00:00
broadcom soc/broadcom/cygnus: Increase romstage SRAM size in memlayout 2018-08-13 12:16:32 +00:00
cavium soc/cn81xx: Add vboot support 2018-08-24 12:29:28 +00:00
imgtec soc/imgtec/pistachio: Get rid of device_t 2018-06-04 09:18:19 +00:00
intel siemens/mc_apl1: Correct the Tx signal from SATA interface 2018-08-31 04:11:43 +00:00
lowrisc riscv: add support for modifying compiler options 2018-07-17 18:09:43 +00:00
mediatek arm64: Factor out common parts of romstage execution flow 2018-08-17 21:29:46 +00:00
nvidia arm64: Remove set_cntfrq() function 2018-08-10 04:16:06 +00:00
qualcomm drivers/i2c: Add i2c TPM support for different stages 2018-08-10 23:25:52 +00:00
rockchip drivers/i2c: Add i2c TPM support for different stages 2018-08-10 23:25:52 +00:00
samsung src: Fix typo 2018-08-10 21:25:53 +00:00
sifive sifive/fu540: add empty sdram init and size functions 2018-07-18 07:54:54 +00:00
ucb riscv: add support for modifying compiler options 2018-07-17 18:09:43 +00:00