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coreboot-kgpe-d16/src/soc/intel
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Lijian Zhao 79152f3c81 soc/intel/cannonlake: Add options for pcie ltr 
FSP can support enable/disable Pci express LTR (Latency Tolerance
Reporting) mechanism through upd interface. Include that into coreboot
side.

BUG=N/A
TEST=N/A

Change-Id: I69b423afa4f81a2d58375734bba07792e08931d5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29642
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-17 07:25:54 +00:00
..
apollolake src: Remove unneeded include <cbfs.h> 2018-11-16 10:26:32 +00:00
baytrail src: Remove unneeded include <cbfs.h> 2018-11-16 10:26:32 +00:00
braswell src: Remove unneeded include <cbmem.h> 2018-11-16 10:56:47 +00:00
broadwell src: Remove unneeded include <cbmem.h> 2018-11-16 10:56:47 +00:00
cannonlake soc/intel/cannonlake: Add options for pcie ltr 2018-11-17 07:25:54 +00:00
common src: Remove unneeded include <cbfs.h> 2018-11-16 10:26:32 +00:00
denverton_ns src: Remove unneeded include <cbmem.h> 2018-11-16 10:56:47 +00:00
fsp_baytrail src: Remove unneeded include <cbmem.h> 2018-11-16 10:56:47 +00:00
fsp_broadwell_de src: Remove unneeded include <lib.h> 2018-11-16 09:50:51 +00:00
icelake src: Remove unneeded include <cbmem.h> 2018-11-16 10:56:47 +00:00
quark src: Remove unneeded include <console/console.h> 2018-11-16 09:50:29 +00:00
skylake SMBIOS: Remove duplicated smbios_memory_type enum 2018-11-16 15:48:04 +00:00
Kconfig src/cpu: Remove dead sourced lines 2018-11-15 10:25:20 +00:00