Arthur Heymans 79a7ad6dda mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6 ... The southbridge has the function disable bits for port 5 and 6 strapped RO to 1 (disable). Change-Id: I2948935d42b9031d61f9e5b3f06b769e68f5a042 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>		2019-01-08 14:28:56 +00:00
..
acpi
arch	usbdebug: Initialize the HW once in CAR stages	2019-01-07 10:36:59 +00:00
commonlib
console	device/pci_early: Fixes for __SIMPLE_DEVICE__	2018-12-30 21:33:26 +00:00
cpu	device: Use pcidev_on_root()	2019-01-06 01:17:54 +00:00
device	amdfam10 boards: Fix regression on dev_find_slot() removal	2019-01-08 02:51:47 +00:00
drivers	usbdebug: Sanity check PCI EHCI location	2019-01-07 10:38:26 +00:00
ec	ec/chromeec: fix LPC read/write for MEC devices	2018-12-28 12:24:52 +00:00
include	usbdebug: Make the EHCI debug console work in the bootblock	2019-01-06 14:05:20 +00:00
lib	src: Get rid of device_t	2019-01-04 12:11:18 +00:00
mainboard	mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6	2019-01-08 14:28:56 +00:00
northbridge	nb/intel/gm45: Remove the C native graphic init	2019-01-07 23:08:41 +00:00
security
soc	soc/intel/icelake: Increase bootblock size	2019-01-08 12:33:54 +00:00
southbridge	intel/lynxpoint: Fix spelling	2019-01-07 10:39:58 +00:00
superio	Kconfig: Unify power-after-failure options	2019-01-06 15:54:19 +00:00
vendorcode	chromeos: Provide watchdog support in verstage	2018-12-21 18:14:20 +00:00
Kconfig	cbmem: Always use EARLY_CBMEM_INIT	2018-12-22 11:49:17 +00:00