coreboot-kgpe-d16/src/soc
Youness Alaoui 696ebc2dbc Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.
The Broadwell SATA controller supports IOBP registers on ports 0 and 1 but
Browell supports up to 4 ports, so we need to support setting IOBP for
ports 2 and 3 as well.
The magic numbers (IOBP SECRT88 and DTLE) for ports 2 and 3 were only
guessed by looking at ports 0 and 1 and extrapolating from there.
Port 3 has been tested (DTLE setting on Librem 13) and confirmed to work
so we can assume that port 2 and 3 magic numbers are valid, but having
someone confirm them (through non-public documents?) would be great.

Change-Id: I59911cfa677749ceea9a544a99b444722392e72d
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/18408
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-22 22:24:50 +01:00
..
broadcom/cygnus spi: Get rid of SPI_ATOMIC_SEQUENCING 2016-12-23 04:54:55 +01:00
dmp/vortex86ex src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
imgtec/pistachio spi: Get rid of SPI_ATOMIC_SEQUENCING 2016-12-23 04:54:55 +01:00
intel Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3. 2017-02-22 22:24:50 +01:00
lowrisc/lowrisc soc/lowrisc: Place CBMEM at top of autodetected RAM 2016-12-06 18:51:13 +01:00
marvell soc/marvell/mvmap2315: Mark mvmap2315_reset() as noreturn 2017-01-12 18:52:11 +01:00
mediatek/mt8173 spi: Get rid of SPI_ATOMIC_SEQUENCING 2016-12-23 04:54:55 +01:00
nvidia spi: Define and use spi_ctrlr structure 2016-12-05 03:29:04 +01:00
qualcomm qualcomm/ipq40xx: add vector operation method to SPI 2017-02-22 17:03:09 +01:00
rdc/r8610 rdc/r8610: Move to src/soc 2016-05-05 20:08:58 +02:00
rockchip rockchip/rk3399: set edp pclk to 25MHz 2017-01-24 09:34:04 +01:00
samsung samsung/exynos5420: Fix test for src < 0 2016-12-16 15:57:56 +01:00
ucb/riscv soc/ucb/riscv: Place CBMEM at top of autodetected RAM 2016-12-06 18:48:28 +01:00