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coreboot-kgpe-d16/src/mainboard/intel/shadowmountain
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Aamir Bohra 7f61e5703b mb/intel/shadowmountain: Add ACPI entry for BT reset GPIO 
Change-Id: Ia9e57f34eceaf1925dc5e3ffa6370ba0241447a4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-03-15 06:09:27 +00:00
..
spd mb/intel/shadowmountain: Add the romstage code 2021-02-22 05:46:58 +00:00
variants/baseboard mb/intel/shadowmountain: Add ACPI entry for BT reset GPIO 2021-03-15 06:09:27 +00:00
board_info.txt
bootblock.c mb/intel/shadowmountain: Add bootblock and verstage code 2021-02-06 09:09:16 +00:00
chromeos.c mb/intel/shadowmountain: Add bootblock and verstage code 2021-02-06 09:09:16 +00:00
chromeos.fmd mb/intel/shadowmountain: Add flash layout 2021-01-28 03:11:35 +00:00
dsdt.asl mb/intel/shadowmountain: Add the ASL code 2021-02-27 09:40:57 +00:00
ec.c mb/intel/shadowmountain: Add the ramstage code 2021-02-27 09:40:47 +00:00
Kconfig mb/intel/shadowmountain: Enable Type-C subsystem 2021-03-12 04:26:39 +00:00
Kconfig.name
mainboard.c mb/intel/shadowmountain: Add the ramstage code 2021-02-27 09:40:47 +00:00
Makefile.inc mb/intel/shadowmountain: Add the ramstage code 2021-02-27 09:40:47 +00:00
romstage.c mb/intel/shadowmountain: Add the romstage code 2021-02-22 05:46:58 +00:00
smihandler.c mb/intel/shadowmountain: Add the ramstage code 2021-02-27 09:40:47 +00:00