Musse Abdullahi ab496bf177 soc/intel/meteorlake: Add B0 stepping CPU ID ... This patch adds CPU ID for B0 stepping (aka ES2). DOC=#723567 TEST=Able to boot on B0 rvp and get correct CPU Name in coreboot log. Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74300 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2023-04-15 12:10:08 +00:00
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cpu_ids.h	soc/intel/meteorlake: Add B0 stepping CPU ID	2023-04-15 12:10:08 +00:00
em64t100_save_state.h
em64t101_save_state.h
fsb.h
l2_cache.h
microcode.h	cpu/intel/microcode: Have API to re-load microcode patch	2022-06-22 12:35:53 +00:00
msr.h
post_codes.h	src: Move POST_BOOTBLOCK_CAR to common postcodes and use it	2023-02-07 10:53:34 +00:00
smm_reloc.h	mb/emulation/qemu-q35: Split smm_close() and smm_lock()	2022-11-17 07:42:55 +00:00
speedstep.h	cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm	2022-12-05 14:22:12 +00:00
turbo.h