0d34a50a36
This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific postcodes into the common postcode list, and uses it for the cache-as-RAM init as needed. Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in most of the others, the values were consolidated into 0x21. This will change the value on some platforms. Any conflicts should get sorted out later in the conversion process. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8527334e679a23006b77a5645f919aea76dd4926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
28 lines
974 B
C
28 lines
974 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef CPU_INTEL_CAR_POST_CODES_H
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#define CPU_INTEL_CAR_POST_CODES_H
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#define POST_SOC_SET_DEF_MTRR_TYPE 0x21
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#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate
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#define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22
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#define POST_SOC_BSP_INIT 0x23
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#define POST_SOC_COUNT_CORES 0x24
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#define POST_SOC_CPU_HYPER_THREADING 0x25
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#define POST_SOC_CPU_SIBLING_DELAY 0x26
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#define POST_SOC_CPU_AP_INIT 0x27
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#define POST_SOC_SET_MTRR_BASE 0x28
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#define POST_SOC_SET_MTRR_MASK 0x29 // Intentional Duplicate
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#define POST_SOC_AP_HALT 0x29
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#define POST_SOC_SET_CAR_BASE 0x2a
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#define POST_SOC_ENABLE_MTRRS 0x2b
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#define POST_SOC_ENABLE_CACHE 0x2c
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#define POST_SOC_DISABLE_CACHE 0x2d
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#define POST_SOC_FILL_CACHE 0x2e
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#define POST_BOOTBLOCK_BEFORE_C_ENTRY 0x2f
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#define POST_POSTCAR_DISABLE_CACHE 0x30
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#define POST_POSTCAR_DISABLE_DEF_MTRR 0x31
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#define POST_POSTCAR_TEARDOWN_DONE 0x32
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#endif
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