c3385070d6
Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/thermal.h>
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#include "chip.h"
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#define MAX_TRIP_TEMP 205
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#define DEFAULT_TRIP_TEMP 50
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static void *pch_thermal_get_bar(struct device *dev)
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{
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uintptr_t bar;
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bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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/*
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* Bits [31:12] are the base address as per EDS for Thermal Device,
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* Don't care about [11:0] bits
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*/
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return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
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}
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static void pch_thermal_set_bar(struct device *dev, uintptr_t tempbar)
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{
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uint8_t pcireg;
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/* Assign Resources to Thermal Device */
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/* Clear BIT 1-2 of Command Register */
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pcireg = pci_read_config8(dev, PCI_COMMAND);
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pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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pci_write_config8(dev, PCI_COMMAND, pcireg);
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/* Program Temporary BAR for Thermal Device */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar);
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pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0);
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/* Enable Bus Master and MMIO Space */
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pcireg = pci_read_config8(dev, PCI_COMMAND);
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pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config8(dev, PCI_COMMAND, pcireg);
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}
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/* PCH Low Temp Threshold (LTT) */
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static uint16_t pch_get_ltt_value(struct device *dev)
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{
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static struct soc_intel_skylake_config *config;
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uint16_t ltt_value;
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uint16_t trip_temp = DEFAULT_TRIP_TEMP;
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config = dev->chip_info;
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if (config->pch_trip_temp)
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trip_temp = config->pch_trip_temp;
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if (trip_temp > MAX_TRIP_TEMP)
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die("Input PCH temp trip is higher than allowed range!");
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/* Trip Point Temp = (LTT / 2 - 50 degree C) */
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ltt_value = (trip_temp + 50) * 2;
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return ltt_value;
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}
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/* Enable thermal sensor power management */
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void pch_thermal_configuration(void)
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{
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uint16_t reg16;
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struct device *dev = PCH_DEV_THERMAL;
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if (!dev) {
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printk(BIOS_ERR, "PCH_DEV_THERMAL device not found!\n");
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return;
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}
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void *thermalbar = pch_thermal_get_bar(dev);
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/* Use default pre-ram bar */
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if (!thermalbar) {
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pch_thermal_set_bar(dev, THERMAL_BASE_ADDRESS);
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thermalbar = (void *)THERMAL_BASE_ADDRESS;
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}
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/* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */
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reg16 = read16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT);
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reg16 &= ~0x1ff;
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/* Low Temp Threshold (LTT) */
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reg16 |= pch_get_ltt_value(dev);
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write16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT, reg16);
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}
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