coreboot-kgpe-d16/src/mainboard/intel/adlrvp
Meera Ravindranath 89356d142b mb/intel/adlrvp_p: Enable TCSS USB ports device path
TEST=Boot RVP, ensure Type C ports operate correctly.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Iadc0df2e6e29a5afbcbb7db1ae0be6546dbcdc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-09-14 14:04:30 +00:00
..
include/baseboard mb/intel/adlrvp: create dynamic power limits mechanism for thermal 2021-08-10 21:22:22 +00:00
spd mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKU 2021-08-13 18:04:02 +00:00
variants mb/intel/adlrvp_p: Enable TCSS USB ports device path 2021-09-14 14:04:30 +00:00
board_id.c
board_id.h
board_info.txt
bootblock.c mb/{google, intel}: Make use of `cpu/intel/cpu_ids.h' 2021-07-19 18:25:42 +00:00
chromeos.c
chromeos.fmd mb/intel/adlrvp: Increase RO/RW region size in chromeos.fmd 2021-05-03 07:42:51 +00:00
devicetree.cb soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default 2021-08-28 18:21:26 +00:00
devicetree_m.cb soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default 2021-08-28 18:21:26 +00:00
dsdt.asl mb/intel/adlrvp: Remove ASL code and enable dynamic SSDT creation for camera ACPI 2021-07-05 10:51:32 +00:00
early_gpio.c mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIO 2021-05-07 09:32:26 +00:00
early_gpio_m.c mb/intel/adlrvp_m: Enable CR50 TPM support over SPI 2021-08-16 14:59:55 +00:00
ec.c
fw_config.c mb/intel/adlrvp: Enable I2S audio codecs on ADL-M RVP 2021-07-21 15:43:16 +00:00
gpio.c
gpio_m.c mb/intel/adlrvp_m: Fix TPM IRQ conflict with I2C4 2021-09-03 16:36:02 +00:00
Kconfig mb/adlrvp: Add new ADL P board variant for MCHP1727 2021-09-13 13:59:45 +00:00
Kconfig.name mb/adlrvp: Add new ADL P board variant for MCHP1727 2021-09-13 13:59:45 +00:00
mainboard.c mb/intel/adlrvp: create dynamic power limits mechanism for thermal 2021-08-10 21:22:22 +00:00
Makefile.inc mb/intel/adlrvp: create dynamic power limits mechanism for thermal 2021-08-10 21:22:22 +00:00
memory.c mb/intel/adlrvp: Add board id for MR DDR5 SKU 2021-06-14 05:55:30 +00:00
ramstage.c mb/intel/adlrvp: Clean up the print message 2021-09-05 19:21:34 +00:00
romstage_fsp_params.c mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKU 2021-08-13 18:04:02 +00:00
smihandler.c