c4f8fbdb11
Add code for panel and backlight configuration. Tested successfully with libgfxinit on Clevo L141CU. Change-Id: If619b28478b4b0d18f28f318c16336e0de76e129 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <commonlib/helpers.h>
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#include <device/device.h>
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#include <device/mmio.h>
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#include <device/pci_def.h>
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#include <device/resource.h>
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#include <drivers/intel/gma/i915_reg.h>
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#include <intelblocks/graphics.h>
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#include <soc/ramstage.h>
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#include <types.h>
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void graphics_soc_panel_init(struct device *dev)
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{
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const struct soc_intel_cannonlake_config *conf = dev->chip_info;
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const struct i915_gpu_panel_config *panel_cfg;
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const struct resource *mmio_res;
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void *mmio;
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uint32_t reg32;
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unsigned int pwm_period, pwm_polarity, pwm_duty;
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if (!conf)
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return;
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panel_cfg = &conf->panel_cfg;
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mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
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if (!mmio_res || !mmio_res->base)
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return;
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mmio = (void *)(uintptr_t)mmio_res->base;
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/* Panel timings */
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reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4;
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reg32 |= PANEL_POWER_RESET;
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write32(mmio + PCH_PP_CONTROL, reg32);
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reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
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reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
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write32(mmio + PCH_PP_ON_DELAYS, reg32);
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reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
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reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
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write32(mmio + PCH_PP_OFF_DELAYS, reg32);
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/* Backlight */
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if (panel_cfg->backlight_pwm_hz) {
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pwm_polarity = panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0;
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pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ, panel_cfg->backlight_pwm_hz);
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pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */
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write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period);
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write32(mmio + BXT_BLC_PWM_CTL(0), pwm_polarity);
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write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty);
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}
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}
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const struct i915_gpu_controller_info *
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intel_igd_get_controller_info(const struct device *const dev)
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{
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const struct soc_intel_cannonlake_config *const chip = dev->chip_info;
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return &chip->gfx;
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}
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