Michael Niewöhner 89fe2f34b4 soc/intel/cnl: use Kconfig to determine PCH type ... We already know the PCH type at build time, so there is no need to do runtime detection. Thus, use Kconfig and drop `get_pch_series()`. Change-Id: I470871af5f5954e91a8135fddf4a2297a514d740 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49874 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-01-24 14:03:33 +00:00
..
acpi	soc/intel/cannonlake: Enable wake from USB in S4	2021-01-11 07:33:13 +00:00
bootblock	soc/intel/cnl: use Kconfig to determine PCH type	2021-01-24 14:03:33 +00:00
include/soc	soc/intel/cnl: use Kconfig to determine PCH type	2021-01-24 14:03:33 +00:00
romstage	{soc,vc,mb}/intel: Drop support for Cannon Lake SoC	2021-01-11 17:23:53 +00:00
acpi.c	ACPI GNVS: Drop most dev_count_cpu()	2021-01-20 09:22:59 +00:00
chip.c	soc/intel: hook up new gpio device in the soc chips	2020-12-30 00:30:04 +00:00
chip.h	{soc,vc,mb}/intel: Drop support for Cannon Lake SoC	2021-01-11 17:23:53 +00:00
cnl_memcfg_init.c
cpu.c	{soc,vc,mb}/intel: Drop support for Cannon Lake SoC	2021-01-11 17:23:53 +00:00
elog.c	ELOG: Add const qualifier for chipset_power_state	2021-01-23 20:18:11 +00:00
finalize.c	soc/intel/{skl,cnl}: drop duplicate PM ACPI timer disabling	2020-11-13 17:18:20 +00:00
fsp_params.c	soc/intel/cannonlake: Allow RP#1 usage for ClkSrc	2021-01-21 11:01:08 +00:00
gpio.c	soc/intel/{skl,cnl}: add NMI_{EN,STS} registers	2020-12-04 00:10:38 +00:00
gpio_cnp_h.c	soc/intel/{skl,cnl}: add NMI_{EN,STS} registers	2020-12-04 00:10:38 +00:00
gpio_common.c
graphics.c	soc/intel/cnl: add panel and backlight configuration code	2021-01-01 21:12:45 +00:00
gspi.c
i2c.c
Kconfig	soc/intel/cnl: add SLP_S0 residency register and enable LPIT support	2021-01-11 20:49:30 +00:00
lockdown.c
lpc.c	soc/intel/cnl: use Kconfig to determine PCH type	2021-01-24 14:03:33 +00:00
Makefile.inc	soc/intel/cometlake: Add ucode for CML-H	2021-01-23 17:00:31 +00:00
me.c	soc/intel/cannonlake: Align cosmetics with Ice Lake	2020-10-12 20:59:17 +00:00
nhlt.c
p2sb.c
pmc.c
pmutil.c	ACPI: Add helpers for CBMEM_ID_POWER_STATE	2021-01-23 20:31:09 +00:00
reset.c	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
sd.c	soc/intel/cannonlake: Align cosmetics with Ice Lake	2020-10-12 20:59:17 +00:00
smihandler.c	soc/intel/cnl: replace the remains of HeciEnabled by device state in dt	2020-11-13 22:30:29 +00:00
smmrelocate.c
spi.c
systemagent.c
uart.c	soc/intel: rename uart_max_index	2021-01-12 23:38:32 +00:00
vr_config.c	soc/intel/cannonlake: Add Iccmax and loadlines for CML-S	2020-12-22 22:21:00 +00:00
xhci.c	soc/intel/common: Adapt XHCI elog driver for reuse	2020-12-10 17:45:47 +00:00