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coreboot-kgpe-d16/src/mainboard/google/brya
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Sumeet Pawnikar 923a403dcf mb/google/brya: set tcc_offset value to 10 
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature. This value is suggested by
Thermal team.

BUGb=b:195706434
BRANCH=None
TEST=Built for brya platform and verified the MSR value

Change-Id: I22573e8ca935d99a16b0876768df169db4e61c4d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57000
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19 13:53:04 +00:00
..
spd mb/google/brya/var/brya0: Use auto-generated Makefile.inc 2021-01-27 15:40:02 +00:00
variants mb/google/brya: set tcc_offset value to 10 2021-08-19 13:53:04 +00:00
board_info.txt
bootblock.c mb/{google, intel}: Make use of `cpu/intel/cpu_ids.h' 2021-07-19 18:25:42 +00:00
chromeos.c mb/google/brya: Finish support for ChromeOS GPIOs 2021-03-08 18:25:11 +00:00
chromeos.fmd mb/google/brya: Reorganize flashmap 2021-03-09 18:45:00 +00:00
dsdt.asl mb/google/brya: Enable WFC 2021-06-01 23:03:12 +00:00
ec.c
Kconfig mb/google/brya: Introduce new baseboard brask 2021-08-03 15:19:40 +00:00
Kconfig.name mb/google/brya: Enable ADL_ENABLE_USB4_PCIE_RESOURCES for primus 2021-08-19 04:02:17 +00:00
mainboard.asl mb/google/brya: Implement SLP_S0_GATE signal 2021-03-18 22:31:36 +00:00
mainboard.c mb/google/brya: create dynamic power limits mechanism for thermal 2021-08-09 15:02:56 +00:00
Makefile.inc mb/google/brya: Introduce new baseboard brask 2021-08-03 15:19:40 +00:00
romstage_spd_cbfs.c mb/google/brya: Introduce new baseboard brask 2021-08-03 15:19:40 +00:00
smihandler.c