8e0bfe263c
Disable PSE loading by default. If left enabled (current default), the EHL coreboot will end up in endless restart loop, due to FSP unable to locate PSE FW image and trigger global reset. However disabling this flag (PchPseEnable) will cause the coreboot to trigger a single reset due to CSE signal (HECI: CSE does not meet required prerequisites). The reason behind this is that FSP need to perform static disabling (power gate) to fully shut down PSE HW, and to do this will need to global reset entire system including CSE. Then PMC will power gate PSE from the start. To avoid this behavior, the best way to disable PSE is to disable via IFWI FIT softstrap (For specific detail can refer to Intel EHL coreboot MR2 release notes). With this, PMC will power gate PSE from the first cold boot and system will boot happily without single reset behavior. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> |
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