Kane Chen 91ea9f0b90 mb/google/fizz: set SataMode to AHCI mode ... For Fizz, the default should be AHCI mode and not RAID mode. Additionally, there is only one drive connector, so attaching several drives for a RAID is hard. BUG=b:70146894 Change-Id: I2a9aa2d6281a916c00ff4659a927f164ba0e0705 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/22837 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>		2017-12-15 06:43:34 +00:00
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acpi	mainboard/google/fizz: Disable DPTF active policy	2017-11-30 17:31:23 +00:00
acpi_tables.c
board_info.txt
bootblock.c
chromeos.c	mb/google/fizz: Set lid status as open	2017-04-24 19:32:24 +02:00
chromeos.fmd	mainboard/google/fizz: Enable separate MRC cache for recovery mode	2017-11-20 23:33:00 +00:00
devicetree.cb	mb/google/fizz: set SataMode to AHCI mode	2017-12-15 06:43:34 +00:00
dsdt.asl
ec.c	ec/google/chromeec: Add library function google_chromeec_events_init	2017-10-08 19:38:28 +00:00
ec.h	mainboard/google/fizz: Enable cros_ec_keyb device	2017-09-26 18:44:16 +00:00
gpio.h	google/fizz: Remove tpm i2c configs from Kconfig	2017-11-25 08:31:55 +00:00
Kconfig	boardid: Switch from Kconfig to weak functions	2017-12-07 01:19:27 +00:00
Kconfig.name
mainboard.c	google/fizz: Set BJ max current and voltage	2017-12-08 17:14:34 +00:00
Makefile.inc	mb/google/*: Use newly added Chrome EC boardid function	2017-09-26 15:20:39 +00:00
ramstage.c
romstage.c	google/fizz: correct memory rcomp settings	2017-11-27 03:55:42 +00:00
smihandler.c