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coreboot-kgpe-d16/src/northbridge/intel/haswell
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Nico Huber 3de303179a {mb,nb,soc}: Remove references to pci_bus_default_ops() 
pci_bus_default_ops() is the default anyway.

Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08 03:01:04 +00:00
..
acpi nb/intel: add IS_ENABLED() around Kconfig symbol references 2017-06-27 17:16:19 +00:00
acpi.c nb/intel/haswell: Generate ACPI DMAR table 2018-03-08 17:49:50 +00:00
bootblock.c PCI ops: MMCONF_SUPPORT_DEFAULT is required 2016-12-07 12:59:28 +01:00
chip.h
early_init.c nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APIC 2018-03-08 19:14:17 +00:00
finalize.c pci: Move inline PCI functions to pci_ops.h 2018-04-20 13:03:54 +00:00
gma.c 3rdparty/lib{hwbase,gfxinit}: Update to latest master 2017-10-28 19:46:17 +00:00
haswell.h nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APIC 2018-03-08 19:14:17 +00:00
Kconfig nb/intel/haswell: Use the common MRC cache driver 2018-02-06 16:13:49 +00:00
Makefile.inc nb/intel/haswell: Use the common MRC cache driver 2018-02-06 16:13:49 +00:00
minihd.c
northbridge.c {mb,nb,soc}: Remove references to pci_bus_default_ops() 2018-05-08 03:01:04 +00:00
pei_data.h Rename __attribute__((packed)) --> __packed 2017-07-13 19:45:59 +00:00
ram_calc.c
raminit.c nb/intel/haswell: Use the common MRC cache driver 2018-02-06 16:13:49 +00:00
raminit.h haswell: add CBMEM_MEMINFO table when initing RAM 2017-06-16 16:08:24 +02:00
report_platform.c