Raul E Rangel 95b3dc3da9 soc/amd/cezanne: Implement PROVIDES_ROM_SHARING ... BUG=none TEST=Build guybrush and verified with the PPR that the register and bits are still the same Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0619f84cf82cbb90ded9dfd58afa6acc9520fb8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>		2021-03-29 18:57:28 +00:00
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amd	soc/amd/cezanne: Implement PROVIDES_ROM_SHARING	2021-03-29 18:57:28 +00:00
cavium	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
example	arch/x86: Move prologue to .init section	2021-01-07 11:02:03 +00:00
intel	soc/intel/alderlake: add processor power limits control support	2021-03-28 16:08:02 +00:00
mediatek	soc/mediatek: Adjust hsa, hbp, hfp packets for MIPI_DSI_MODE_LINE_END	2021-03-27 10:03:41 +00:00
nvidia	cbfs: Replace more instances of cbfs_boot_locate() with newer APIs	2021-03-17 08:10:20 +00:00
qualcomm	cbfs: Remove prog_locate() for payloads (SELF and FIT)	2021-03-17 00:13:53 +00:00
rockchip	soc/rockchip/rk3399/sdram: Add channel to error message	2021-03-04 01:22:10 +00:00
samsung	cbfs: Pull handling of the CBFS_CACHE mem_pool into CBFS core	2021-03-08 22:31:29 +00:00
sifive	memlayout: Store region sizes as separate symbols	2021-02-19 08:39:26 +00:00
ti	soc/ti/am335x/header.c: Add missing include	2021-02-03 08:55:15 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00