Eric Lai 4ea47c32b0 soc/intel/alderlake: Update chipset.cb for TCSS and USB ... Follow TGL chipset.cb to add alias for TCSS and USB ports. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/48793 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-12-29 17:25:27 +00:00
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acpi	soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD	2020-11-20 00:12:09 +00:00
bootblock	soc/intel/common/dmi: Move DMI defines into DMI driver header	2020-12-09 14:23:15 +00:00
include/soc	soc/intel/alderlake: Add SPI DMI Destination ID	2020-12-23 03:28:47 +00:00
romstage	src/soc/intel/alderlake: Enable the PCH HDA	2020-12-04 07:05:43 +00:00
acpi.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
chip.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
chip.h	soc/intel/alderlake: Drop unreferenced devicetree settings	2020-12-14 08:18:06 +00:00
chipset.cb	soc/intel/alderlake: Update chipset.cb for TCSS and USB	2020-12-29 17:25:27 +00:00
cpu.c	soc/intel: deduplicate ACPI timer emulation	2020-10-28 21:28:19 +00:00
elog.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
espi.c	soc/intel/alderlake/ramstage: Fix compilation issue	2020-10-06 12:30:15 +00:00
finalize.c	soc/intel/*: drop useless XTAL shutdown qualification code	2020-10-19 07:09:12 +00:00
fsp_params.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
gpio.c	soc/intel/alderlake: Add GPIOs for Alder Lake SOC	2020-09-27 03:03:25 +00:00
gspi.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
i2c.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
Kconfig	soc/intel/alderlake: Update chipset.cb for TCSS and USB	2020-12-29 17:25:27 +00:00
lockdown.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
Makefile.inc	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
me.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
meminit.c	soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration	2020-11-29 14:39:06 +00:00
p2sb.c	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	2020-09-15 15:13:50 +00:00
pmc.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
pmutil.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
reset.c	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
smihandler.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
smmrelocate.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
soundwire.c	mb/intel: Enable ALC711 Audio codec over SNDW0 link	2020-11-07 08:55:53 +00:00
spi.c	soc/intel/alderlake: Add SPI DMI Destination ID	2020-12-23 03:28:47 +00:00
systemagent.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
uart.c	soc/intel/alderlake: Update UART0 GPIO as per latest schematics	2020-11-23 03:37:33 +00:00